Lithography masks (or “reticles”) are key elements used in the production of integrated circuits (ICs). A portion of an IC layout data file (typically a representation of a physical layer, such as a metal layer or a polysilicon layer, of the final IC) is etched into a thin chrome layer formed over a glass plate to form a reticle. This reticle pattern (“reticle layout”) is then exposed onto a layer of photosensitive resist on the surface of the wafer. Finally, the top surface of the wafer is chemically etched away in the areas not covered by the photoresist, thereby transferring the reticle layout onto the wafer. This transference process is known as lithography. The accuracy of the pattern formed on the wafer (“printed layout”) significantly affects both process yield and the performance of the final IC.
The actual reticle formation process typically involves the steps of exposing the reticle pattern into a layer of resist on a blank reticle, developing the resist pattern (i.e. removing the exposed or unexposed portions of the resist layer), etching the resist pattern into the chrome layer of the reticle, inspecting the chrome pattern, and repairing any defects found in the chrome pattern.
While an optical projection (e.g. a laser beam scanner) system can be used to expose the reticle pattern into the resist layer, complex modern layouts are typically written by an electron beam scanner. Two main techniques are used in the exposing step of the electron beam writing process—raster scan and vector scan. In a raster scan system, the output of the scanner is moved in horizontal passes across the entire reticle and shifted an increment downwards after each pass, with the electron beam being applied to regions where the resist is to be exposed. The “spot size” of the electron beam can be set small to enable precise scanning of the reticle layout. However, a larger spot size is desirable to speed up the scanning process. Therefore, accuracy and throughput must be traded off against one another in conventional raster scan writing processes. An example of a raster scan system is the MEBES family of tools (models 4000, 4500, 5000, 5500) from Etec Systems, Inc. (a subsidiary of Applied Materials Inc.).
In a vector scan system, the electron beam is moved directly to regions that are to be exposed. Most modern vector scan systems employ a shaped spot technique, in which the electron beam is formed into various primitive shapes (rectangles and triangles). The regions to be exposed are decomposed into primitives (rectangles and triangles), and each primitive is then exposed in a single shot by the electron beam, which is shaped to match the primitive being exposed. Vector scanning can be more efficient than raster scanning since the write tool does not have to scan the entire surface of the reticle. Therefore, a sparse layout will be written much faster on a vector scan system than a raster scan system. However, individually targeting the many features in a dense, complex layout can make a vector scan system take longer to write the layout than a raster scan system. And as with raster scanning, beam spot size selection still must balance accuracy and throughput. Examples of vector scan systems include the JBX-6000FS from JEOL, Inc., the Vectorbeam from Leica Lithography Systems, Ltd., and the HL-800, HL-900, and HL-950 tools from Hitachi.
After the resist layer has been exposed, the resist pattern is developed. A negative resist is converted by the exposing radiation or electron beam into an insoluble state, and the developing process removes all the non-exposed portions of the resist layer. Exposure of a positive resist transforms the resist from an insoluble state into a soluble state, and the developing process then removes all the exposed portions of the resist layer. The chrome layer of the reticle is then etched through the pattern formed in the resist layer, after which the remaining resist is stripped from the reticle.
Next, an inspection tool checks to ensure that the IC layout has been properly written to the reticle. An optical image of the mask layout is checked against the original IC layout data, which may be modified to more accurately represent the expected output. Alternatively, for a reticle comprising multiple identical die layouts, the optical images of the individual die layouts can be compared against each other. Regardless of the specific comparison technique, the inspection sensitivity (i.e. the precision with which inspection is performed) is a key parameter of the inspection process. Because the entire reticle is typically inspected, a high inspection sensitivity can significantly increase the time required complete the process. A lower inspection sensitivity can reduce the inspection time, but may miss defects or deviations in the reticle layout. Therefore, conventional inspection techniques are faced with a tradeoff between inspection sensitivity and efficiency.
Finally, defects and deviations detected during the inspection process are corrected. A laser tool (laser zapping or laser assisted deposition) is often used for rapid corrections, while a focused ion beam tool (ion milling or ion-assisted etch or deposition) provides more precise, yet slower, modifications.
FIG. 1 shows a technique proposed in an effort to address these mask making and inspection issues as described by Glasser et al., in PCT Patent Application No. PCT/US99/30240, filed Dec. 17, 1999. FIG. 1 shows a portion of an original IC layout comprising a diffusion region 110 and a polysilicon region 120. A critical region 130 of polysilicon region 120 is identified where polysilicon region 120 overlies diffusion region 110. This overlap of polysilicon region 120 and diffusion region 110 represents a transistor gate to be formed in the final IC device. As a key feature of the final IC, the gate requires a high degree of precision to ensure proper performance of the transistor in the final IC device. However, other features of the IC layout may not require such a high degree of dimensional accuracy. For example, interconnects and contact pads can occupy a wider tolerance band than transistor gates without significantly affecting device performance. Consequently, by flagging critical regions such as region 130, special care can be directed towards those regions during mask making and/or inspection (e.g. very high inspection sensitivity). Less stringent standards (e.g. lower inspection sensitivity) can then be applied to the remaining regions to improve throughput. Therefore, Glasser et al. attempts to efficiently form a high-yield reticle, i.e. a reticle that will produce critical features of the final IC accurately and consistently.
However, even though a particular portion of the original IC layout may correspond to a key feature in the final IC device, the actual creation of the key feature typically depends on much more than just the representation of that particular portion of the IC layout in a reticle. The mask-writing processes used to transfer the layout data to a reticle and the lithographic procedures used to print the reticle layout on a wafer are subject to “proximity effects”, wherein the final dimensions of the features formed during the transference processes are affected by the presence or absence of neighboring features. For example, during optical lithography, the width of closely spaced lines may be different from the width of isolated lines, even if all the lines have the same width in the reticle. Also, the dimensions and regularity of a printed image can be affected by portions of adjacent features or even by nearby defects.
An example of a defect-induced proximity effect is shown in FIGS. 2a and 2b. FIG. 2a shows a portion of a polysilicon layer reticle 200 that includes a reticle feature 210. Reticle feature 210 includes a critical region 211 (identified according to the technique of Glasser et al.; i.e. flagging the portion of reticle feature 210 that overlies a diffusion region in the original IC layout) that corresponds to a transistor gate to be formed in the final IC device. Special attention can then be paid to critical region 211 during formation and inspection of reticle 200.
However, reticle 200 also includes a defect 212; i.e. an unintended marking in the opaque (chrome) layer of the reticle. Because regions outside of critical region 211 are written and inspected with less care than critical region 211 as taught by Glasser et al., defects like defect 212 are more likely to be created and be undetected in regions outside of critical region 211. FIG. 2b shows portion of a wafer 220 that includes a polysilicon feature 230 that might be produced from a lithography step using reticle 200. Polysilicon feature 230 includes an actual gate profile 221 that deviates from a desired gate profile 240. Actual gate profile 221 is created because of the proximity effects between reticle feature 210 and reticle defect 212 during lithography. Therefore, despite the identification of the critical region of the original IC layout and subsequent care focused on that critical region during both the reticle making and reticle inspecting steps, the final IC structure is undesirably deformed.
In addition, there may be purposely-added features outside of critical region 211 that play an important role in the formation of the final transistor gate. A technique known as optical proximity correction (OPC) has been developed in which features are introduced around (or modifications are made to) a critical layout feature to “precompensate” for predicted deformations during the lithography process. These OPC features and modifications must be reproduced with the same degree of accuracy as the actual layout feature of interest to ensure their proper effect. Similarly, original layout features adjacent to the critical feature must also be accurately formed so that their effects can be reliably taken into account when incorporating OPC features. However, because the critical region only includes the critical feature itself, these influential external features will not receive the same degree of care in construction as the critical feature, often resulting in a less-than-desired final IC accuracy. Accordingly, it is desirable to provide a method for ensuring accurate formation and inspection of reticles that does not allow proximity effects to introduce unexpected deviations in the final IC features.